1. Field of the Invention
The present invention relates to a driving circuit of a display device and a control system of the driving circuit. More particularly, the invention relates to an active matrix light emitting device comprising a thin film transistor formed over an insulating substrate, wherein each pixel of the display device includes a plurality of volatile or non-volatile memory holding devices each including the thin film transistor. In addition, the invention relates to an active matrix display device using a light emitting element such as an organic electroluminescence (EL) element as a display element of the display device.
2. Description of Related Art
FIG. 12 illustrates an example of a conventional digital display device. A source signal line driving circuit 101, gate signal line driving circuits 102, a shift register circuit 103, a first latch circuit 104, a second latch circuit 105, a power supply line 106, a pixel portion 107 and the like are disposed. The source signal line driving circuit 101 has a configuration as shown in FIG. 13. Note that the gate signal line driving circuits 102 are disposed on both of the right and left sides of the pixel portion in FIG. 12.
The operation thereof is described in brief with reference to FIGS. 12 and 13. First, a clock signal (S-CLK and S-CLKb) and a start pulse (S-SP) are inputted to the shift register circuit 103 (represented by SR(201) in FIG. 13), and sampling pulses are sequentially outputted. Subsequently, the sampling pulses are inputted to the first latch circuit 104 (represented by LAT1(202) in FIG. 13), whereby all of digital video signals (Digital Data) inputted to the first latch circuit 104 are held therein. Once holding of each of one-bit digital video signals for one horizontal cycle is completed in the first latch circuit 104, the digital video signals held in the first latch circuit 104 are transferred to the second latch circuit 105 (represented by LAT2(203) in FIG. 13) all at once in accordance with the input of a latch signal (Latch Pulse).
Meanwhile in the gate signal line driving circuits 102, a gate side clock signal (G-CLK) and a gate side start pulse (G-SP) are inputted to a shift register (not shown) therein. The shift register sequentially outputs pulses based on the input signals. These pulses are outputted as gate signal line selection pulses, whereby gate signal lines are sequentially selected.
Data transferred to the second latch circuit 105 of the source signal line driving circuit 101 is written to a pixel (represented by Pixel(204) in FIG. 13) in columns that are selected by the gate signal line selection pulses.
The drive of the pixel portion 107 is described now. FIG. 14 illustrates a part of the pixel portion 107 in FIG. 12. FIG. 14A illustrates a matrix of 3×3 pixels. A portion surrounded by a dotted frame 300 corresponds to one pixel, which is shown in an enlarged view of FIG. 14B. When a voltage is applied to the gate electrode of a switching TFT 301, the switching TFT 301 is turned ON. Then, a signal (voltage) of a source signal line 306 is accumulated in a storage capacitor 304. A voltage of the storage capacitor 304 is the gate-source voltage VGS of an EL driving TFT 302, therefore, a current corresponding to the voltage of the storage capacitor 304 flows into the EL driving TFT 302 and an EL element 303. Consequently, the EL element 303 emits light.
When a gate signal line 305 is not selected, the gate of the switching TFT 301 is closed, and the switching TFT 301 is thus turned OFF. At this time, a charge accumulated in the storage capacitor 304 is held. Accordingly, the VGS of the EL driving TFT 302 remains to be held, and a current corresponding to the VGS keeps on flowing into the EL element 303 through the EL driving TFT 302. Note that one end of the storage capacitor 304 is connected to a power supply line 307 in FIG. 14B, however, an alternative dedicated wiring may be used.
As for the drive and the like of an EL element, various reports have been given so far (see Non-Patent Documents 1 to 3, for example).
Non-Patent Document 1
SID99 Digest: P372: “Current Status and future of Light-Emitting Polymer Display Driven by Poly-Si TFT”
Non-Patent Document 2
ASIA DISPLAY98: P217: “High Resolution Light Emitting Polymer Display Driven by Low Temperature Polysilicon Thin Film Transistor with Integrated Driver”
Non-Patent Document 3
Euro Display99 Late News: P27: “3.8Green OLED with Low Temperature Poly-Si TFT”
Now, a gray scale method of an EL element is described. Among gray scale methods of an EL element, there is known a time gray scale method. The time gray scale method is a method in which lighting period of an EL element is controlled, the time length of which is utilized to express gray scales. That is, one frame period is divided into a plurality of sub-frame periods, and the number and length of the lighting sub-frame periods are controlled to express gray scales.
Referring now to FIG. 15, a drive timing of a circuit using the time gray scale method is described in brief. This is an example where a frame frequency is set at 60 [MHz] and a time gray scale method is applied to a light emitting device having the pixel density of VGA (640×480 pixels) in order to obtain a 3-bit gray scale. As for a source signal line driving circuit, the circuit shown in FIG. 13 is utilized. A period during which one screen is written is referred to as one frame period.
According to the time gray scale method, as shown in FIG. 15A, one frame period is divided into sub-frame periods corresponding to the number of bits for the gray scales. Since 3-bit gray scale is employed here, one frame period is divided into three sub-frame periods (SF1, SF2 and SF3) (FIG. 15B). One sub-frame period is further divided into an address period (Ta) and a sustain (lighting) period (Ts) (FIG. 15B). A sustain period in SF1 is referred to as TS1. Similarly, sustain periods in SF2 and SF3 are referred to as TS2 and TS3 respectively. In the address period, image signals for one frame are written to pixels, therefore, the address period is the same in length in each of the sub-frame periods (FIG. 15C). Sustain periods satisfies the following relation having the second power: TS1:TS2:TS3=22:21:20=4:2:1.
In the address period, gate signals are selected from the first row in sequence, and digital video signals are sequentially written to the respective pixels. In the sustain (lighting) periods TS1 to TS2, luminance is controlled according to the length of the total lighting periods within one frame period, by controlling an EL element to emit light or not. In this example, 23=8-type lengths of lighting periods can be obtained by the combination of lighting sustain (lighting) periods, therefore, 8 gray scales can be displayed. By utilizing the length of the lighting periods, gray scale display is performed. In the case of increasing the number of gray scales, the division number of one frame may be increased.
In order to perform display by dividing image data for one frame into a plurality of sub-frames like the aforementioned time gray scale method, digital video signals received from outside of the display device is required to be transferred to the display device at an appropriate timing. Therefore, a circuit for modifying the receive timing of digital video signals into the transfer timing thereof to the display device is provided outside of the display device.